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donna tartt the secret history downloadQ:
How to check if a signal is connected in VHDL?
I am trying to check if the signal is connected, or not, when a new value of the signal will be read.
I have a reg file to read it, and I will read if the signal is connected to the reg or not.
For example:
signal reg_val: STD_LOGIC_VECTOR(3 downto 0);
Is there any way to check it in VHDL?
Or should I read this file everytime a value is changed, and save it in a reg file?
This code will be run on a Zynq 7045 SoC.
A:
You can use the process interface to define the duration of a process, and read the register at the end of the process.
signal reg_val: STD_LOGIC_VECTOR(3 downto 0);
process(clk_i)
begin
if rising_edge(clk_i) then
reg_val ;
end if;
end process;
In some cases you may want to do the reading on the falling edge, to ensure that values are latched:
process(clk_i)
begin
if falling_edge(clk_i) then
reg_val ;
end if;
end process;
This last process can be coded into a subprocess of your main process.
EDIT
You can also use a shadow register:
signal reg_val_shadow: STD_LOGIC_VECTOR(3 downto 0);
signal reg_val: STD_LOGIC_VECTOR(3 downto 0);
process(clk_i)
begin
if rising_edge(clk_i) then
reg_val ;
end if;
if falling_edge(clk_i) then
reg_val_shadow ;
end if;
end process; ac619d1d87
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